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Experienced SoC/IP/MCU Design Verification Engineer

Job description

  • Responsibilities will include the designing and verification of digital circuits, system-on-chip, and embedded microcontroller systems, definition of verification plans, development of test bench and verification components and the implementation of test scenarios at system and module level.
  • Communicate with customers and others team for technical related issue and input/output requirement.

Join to develop ONE of the following fields:

  1. System-on-chip (SoC) for Car Infotainment, ADAS application
    • Designing, Integrating whole system including processor, bus, peripheral
    • Verification at both module and system level
  2. Microcontroller (MCU) for Automotive (Engine control, Chassis control, ..,etc)
    • Designing, Integrating whole system including microcontroller, peripheral
    • Verification at both module and system level
  3. IP including Processor and Designing platform for SoC, MCU development
    • Integrating of ARM® related Processor Core
    • Designing of Renesas in-house Processor Core
    • Designing of keys Multimedia IP (Video Signal Processor, Video Encoder/Decorder)
    • Designing of Simulation Platform for accelerating SoC/MCU development, early software development, error simulation, performance evaluation.

Job requirement

  • Understanding about Logic design and verification at all stages, including block/system level functional simulation, formal verification, synthesis, and timing analysis
  • Functional Safety Experience (ISO 26262) is a strong plus
  • Good at both written and oral English communication
  • Good team working skill and good relationship with the others
  • Bachelor or Master Degree in Information Technology/ Computer Engineering/ Computer Science/ Telecoms/ Electronics
  • At least 3 years’ design experience in semiconductor especially in logic design and verification of SOC, MCU, IP, CPU
  • Experience in scripting languages (PERL, shell, etc.)
  • Hardware Verification languages (Verilog, SystemVerilog), SystemVerilog Assertion (SVA), Verification methodology (UVM, VMM)
  • Solid knowledge in using EDA tool (ex: VCS/NC, Design-Compiler, Formality/Conformal)
  • Start working date: As soon as possible

Compensation and benefit package

  • Competitive salary in labor market
  • Performance bonus (2 times/ year, max. 3 months’ salary/ time)
  • Recognition award
  • Commuting allowance
  • Overtime allowance
  • Free lunch
  • Compulsory insurances and private insurances
  • Seniority welfare
  • 15+ days for annual leave
  • Flexible working time
  • Work at home
  • Opportunity for promotion
  • Challenging projects with cutting edge technology
  • Excellent training program for career advancement
  • Professional working environment of team work, fair assessment, talented and friendly people

Interested candidates can send resume to jobs@rvc.renesas.com.