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Experienced Logic Design & Verification Engineer

Job description

  • Participate in developing of the System IPs (Supply clock/reset, operation mode, Power supply, Low voltage detect, etc.) used for general purpose MCU.
  • Participate in developing of peripheral IP design, IP integration and whole chip level verification.
  • IP/Chip level synthesis and None-function verification.
  • FPGA development and evaluation.

Job requirement

  • Bachelor degree or above in relevant majors
  • From 2 years’ experience in relevant field
  • Experience in functional verification with Synopsys/Cadence tool
  • Have fundamental knowledge about System control in MCU
  • Have knowledge about AMBA buses, ARM CPU
  • Having experience in working with FPGA, UVM, USB, PCIe, STA will be a plus
  • Good at both written and spoken English

Expected starting date: As soon as possible

Compensation and benefit package

  • Competitive salary in labor market
  • Attractive performance bonus (twice a year)
  • Recognition award
  • Commuting allowance
  • Overtime allowance
  • Free lunch
  • Compulsory insurances and private insurances for employee and family members
  • Seniority welfare
  • 14+ days for annual leave
  • Flexible working time
  • Opportunity for promotion
  • Challenging projects with cutting edge technology
  • Excellent training program for career advancement
  • Professional working environment of team work, fair assessment, talented and friendly people

Interested candidates can send updated CV to jobs@rvc.renesas.com.

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